The three-dimensional (3D) integration of two or more semiconductor structures can produce a number of benefits to microelectronic applications. For example, 3D integration of microelectronic components can result in improved electrical performance and power consumption while reducing the area of the device footprint. See, for example, P. Garrou et al., “The Handbook of 3D Integration,” Wiley-VCH (2008).
The 3D integration of semiconductor structures may take place by the attachment of a semiconductor die to one or more additional semiconductor dice (i.e., die-to-die (D2D)), a semiconductor die to one or more semiconductor wafers (i.e., die-to-wafer (D2W)), as well as a semiconductor wafer to one or more additional semiconductor wafers (i.e., wafer-to-wafer (W2W)), or a combination thereof.
The bonding techniques used in bonding one semiconductor structure to another semiconductor structure may be categorized in different ways, one being whether a layer of intermediate material is provided between the two semiconductor structures to bond them together, and the second being whether the bonding interface allows electrons (i.e., electrical current) to pass through the interface. So called “direct bonding methods” are methods in which a direct solid-to-solid chemical bond is established between two semiconductor structures to bond them together without using an intermediate bonding material between the two semiconductor structures to bond them together. Direct metal-to-metal bonding methods have been developed for bonding metal material at a surface of a first semiconductor structure to metal material at a surface of a second semiconductor structure.
Direct metal-to-metal bonding methods may also be categorized by the temperature range in which each is carried out. For example, some direct metal-to-metal bonding methods are carried out at relatively high temperatures resulting in at least partial melting of the metal material at the bonding interface. Such direct bonding processes may be undesirable for use in bonding processed semiconductor structures that include one or more device structures, as the relatively high temperatures may adversely affect the earlier formed device structures.
“Thermo-compression bonding” methods are direct bonding methods in which pressure is applied between the bonding surfaces at elevated temperatures between two hundred degrees Celsius (200° C.) and about five hundred degrees Celsius (500° C.), and often between about three hundred degrees Celsius (300° C.) and about four hundred degrees Celsius (400° C.).
Additional direct bonding methods have been developed that may be carried out at temperatures of two hundred degrees Celsius (200° C.) or less. Such direct bonding processes carried out at temperatures of two hundred degrees Celsius (200° C.) or less are referred to herein as “ultra-low temperature” direct bonding methods. Ultra-low temperature direct bonding methods may be carried out by careful removal of surface impurities and surface compounds (e.g., native oxides), and by increasing the area of intimate contact between the two surfaces at the atomic scale. The area of intimate contact between the two surfaces is generally accomplished by polishing the bonding surfaces to reduce the surface roughness up to values close to the atomic scale, by applying pressure between the bonding surfaces resulting in plastic deformation, or by both polishing the bonding surfaces and applying pressure to attain such plastic deformation.
Some ultra-low temperature direct bonding methods may be carried out without applying pressure between the bonding surfaces at the bonding interface, although pressure may be applied between the bonding surfaces at the bonding interface in other ultra-low temperature direct bonding methods in order to achieve suitable bond strength at the bonding interface. Ultra-low temperature direct bonding methods in which pressure is applied between the bonding surfaces are often referred to in the art as “surface-assisted bonding” or “SAB” methods. Thus, as used herein, the terms “surface-assisted bonding” and “SAB” mean and include any direct bonding process in which a first material is directly bonded to a second material by abutting the first material against the second material and applying pressure between the bonding surfaces at the bonding interface at a temperature of two hundred degrees Celsius (200° C.) or less.
Silicon (Si) and glass substrates are commonly perceived as base substrates on which semiconductor devices may be fabricated to enable high bandwidth performance, and for use in first level heterogeneous three-dimensional integration. Interposes are generally planar structures that comprise layers of material, which are interposed between two or more different dice and/or wafers in three-dimensional integration processes. Interposers are used in intermediate processing steps during three-dimensional integrated circuit (3D-IC) integration. The main drivers for silicon interposers are the greater need for high-density chip-to-package interconnects, coefficient of thermal expansion (CTE) matching (e.g., Si on Si), and a greater emphasis on integrating passive devices (e.g., resistors, inductors etc.) into the interposer. For example, interposers may incorporate through substrate vias (TSVs), as well as decoupling capacitors and voltage regulators. In addition, significantly reduced form factors may be achieved on a silicon interposer.
Commonly, silicon interposers are thinned after the formation of the through substrate vias (TSVs) and redistribution layers (RDL) in and on the silicon interposers. Such thinning processes often involve wastage of expensive silicon material. In addition, interposers are usually thinned with copper-filled TSVs and RDL layers. Mechanical strain may build in the interposer after fabrication of the TSVs and RDL layers, and after thinning the interposer. This strain may cause warping of the interposer and may result in fracture or other mechanical damage to the interposer. A warped interposer may also warp the Known Good Die (KGD) that may be mounted upon it, thus significantly affecting the yield of operable devices fabricated on or over the interposer.